1. Field of the Invention
The invention lies in the field of semiconductor manufacture. Specifically, the invention relates to a nonvolatile memory cell having source and drain regions formed in a surface of a semiconductor substrate and spaced apart from one another by a channel region. A fully insulated storage gate electrode is implemented as a cup in a recess of the semiconductor substrate. A control gate electrode, which for capacitive coupling with the storage gate electrode protrudes into the substrate recess. The substrate recess receiving the gate electrode is formed between the source and the drain region.
Typical nonvolatile memory cells are based on what is known as the floating gate (FG) concept. The term floating gate will be used below for the storage gate electrode, for storing a charge. In the floating gate concept, an electrically fully insulated gate, namely the floating gate, which is typically of polycrystalline silicon, forms the actual storage gate. This floating gate is capacitively coupled to a further gate, namely the control gate (CG), or the control gate electrode, and is controlled by it. The floating gate and the control gate are located in two different planes, which are separated from one another by an insulation layer, such as a silicon dioxide layer. The control gate, like the floating gate, also typically comprises polycrystalline silicon.
Because of the high programming voltages required in memories with such memory cells, the capacitive coupling of this voltage to the floating gate should be as high as possible, which can be attained by means of correspondingly large overlapping surface areas between the floating gate and the control gate. In other words, the region in which the floating gate and the control gate overlap should be designed to be as large as possible. Clearly, this need is in conflict with the general demand for increasing the scale of integration, because especially by forming lateral overlapping regions between the floating gate and the control gate, valuable chip area is lost.
A nonvolatile memory cell as generically described in the introductory paragraph is known from U.S. Pat. No. 5,392,237 to Iida. With the cup-shaped recess in the semiconductor substrate there, and the storage gate and control gate electrodes formed in it, a memory cell with small lateral dimensions and an increased degree of coupling between the storage gate and control gate electrodes is obtained. However, there, the transistor channel forms into the substrate, around the recess, because there is a thick oxide film on the substrate surface. Increasing the coupling factor cannot be achieved by lengthening the recess in this known memory cell, however, because the coupling of the storage gate electrode to the substrate increases to the same extent as its coupling to the control gate electrode.
A nonvolatile memory cell with an improved coupling factor over conventional memory cells is known from JP-A 61085468 (Patent Abstracts of Japan). However, there only a part of the storage gate electrode region, which protrudes past the region of the transistor channel, is disposed in an recess, rather than the entire storage gate electrode. Otherwise, that memory cell is of conventional design.
Memory cells of this type are also known from U.S. Pat. No. 4,814,840 to Kameda and U.S. Pat. No. 5,045,490 to Esguivel et al. There, however, the entire portion of the storage gate electrode that protrudes past the transistor region is disposed in trenches disposed in the substrate on both sides of a channel, and one trench is used for two adjacent memory cells.
A laterally embodied overlapping region between the floating gate and the control gate is described for instance by Y. S.
Hisamune et al., Int. Electron Dev. Meeting 1993 (IEDM), Washington, pages 19-22.
To attain the large overlapping region between the floating gate and the control gate that is desired yet still economize on chip area, the idea has also already been proposed of integrating nonvolatile memory cells vertically in a trench structure. Such a concept, in which the drain is placed on top of a trench and the source at the bottom, for instance, so that the transistor channel extends perpendicular to the chip surface, along the wall of the trench, is explained for instance by H. P. Pein et al., IEDM 93, pages 11-14. However, for construction reasons, the structure shown there does not have a very high capacitive coupling.
Better capacitive coupling is attained if the side wall of the polycrystalline silicon of the floating gate is utilized. This concept, but in which the topography of the memory cell is higher, is described for instance by S. Aritome et al., IEDM 94, San Francisco, pages 61-64, or S. Aritome et al., IEDM 95, Washington, pages 275-78.